The present invention relates to DC offset calibration apparatus, and more particularly, to DC offset calibration apparatus for calibrating a DC offset of a gain stage.
In wireless communication applications, a super-heterodyne architecture is widely utilized in conventional RF transceivers. The super-heterodyne transceiver utilizes a costly and volume-consume IF SAW filter to improve performance. This results in increased cost and complexity in system designs.
Recently, in many RF transceivers, the super-heterodyne architecture is replaced with another architecture called “direct conversion” to solve the aforementioned drawbacks. The direct conversion architecture, which is also known as zero IF architecture, directly converts an incoming RF signal into a base-band signal. In contrast to the conventional super-heterodyne architecture, the direct conversion transceiver does not require certain components such as costly SAW filters, IF to base-band converting circuits, and image reject filters. Therefore, the required cost and volume are reduced.
However, the undesirable DC offset more apparently affects the performance of the direct conversion transceiver. The DC offset will distort the output signal of mixers of the transceiver in the frequency band of interested. Then the distorted output signal might saturate the following signal stages such as the analog-to-digital converter (ADC) and degrade the performance of the receiver.
In U.S. Pat. No. 6,225,848, entitled: “Method and Apparatus for Settling and Maintaining DC Offset” and U.S. Pat. No. 6,356,217, entitled: “Enhanced DC Offset Correction Through Bandwidth and Clock Speed Selection,” Tilley et al. disclose architectures for calibrating the DC offset in a radio receiver by utilizing a DC offset correcting loop. In the disclosed DC offset correcting loop, a binary search algorithm is employed to adjust the output voltage of a digital-to-analog converter (DAC) to achieve the DC offset correction. Furthermore, additional voltage DACs and operational transconductance amplifiers (OTAs) are required to improve accuracy of the DC offset correction.
Unfortunately, the correction precision is restricted by the resolution of the voltage DAC. The fine enough resolution of the voltage DAC is hard to achieve, thus the implementation of the transceiver will be compromised to be more costly.